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ftg for intel pentium 4 cpu and chipsets cy28344 rev 1.0, november 21, 2006 page 1 of 21 2200 laurelwood road, santa clara, ca 95054 tel: (408) 855-0555 fax:(408) 855-0550 www.spectralinear.com features ?c ompatible to intel? ck-titan and ck-408 clock synthesizer/driver specifications system frequency synthesizer for intel brookdale (845) and brookdale g pentium? 4 chipsets programmable clock output frequency with less than 1mhz increment integrated fail-safe watchdog timer for system recovery automatically switch to hw-selected or sw-programmed clock frequency when watchdog timer time-out capable of generating sy stem reset after a watchdog timer time-out occurs or a change in output fre quency via smbus interface support smbus byte read/write and block read/write operations to simplify system bios development vendor id and revision id support programmable drive strength support programmable output skew support power management control inputs ? available in 48-pin ssop cpu 3v66 pci ref 48m 3 4 9 1 2 ~ block diagram vdd_ref cpu0:2, cpu0:2#, xtal pll ref freq x2 x1 vdd_pci osc sclk pll 1 smbus logic vdd_48mhz sdata vdd_3v66 divider network vdd_cpu pll2 fs0:4 2 vttpwrgd/pd# ref_2x vdd_ref x1 x2 gnd_ref ^fs0/pci_f0 ^fs1/pci_f1 vdd_pci gnd_pci pci0 pci1 pci2 pci3 vdd_pci gnd_pci pci4 pci5 pci6 vdd_3v66 gnd_3v66 3v66_1 3v66_2 3v66_3 rst# vdd_core 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 28 27 26 25 32 31 30 29 ref_2x/fs2^ cpu0 cpu0# vdd_cpu cpu1 cpu1# gnd_cpu vdd_cpu cpu2 cpu2# multsel0 iref gnd_cpu 48mhz/fs3^ 24_48mhz vdd_48mhz gnd_48mhz 3v66_0/vch_clk/fs4^ vdd_3v66 gnd_3v66 sclk sdata vttpwrgd/pd#* gnd_core multsel0 3v66_1:3 pci_f0:1 pci0:6 48mhz 24_48mhz rst# note: 1. signals marked with ?*? and ?^,? respectively, have internal pull-up and pull-down resistors. vdd_3v66 3v66_0/vch_clk cy28344 ssop-48 pin configuration [1]
cy28344 rev 1.0, november 21, 2006 page 2 of 21 pin definitions pin name pin no. pin type pin description x1 2 i crystal connection or external reference frequency input: this pin has dual functions. it can be used as an external 14.318-mhz crystal connection or as an external reference frequency input. x2 3 o crystal connection: connection for an external 14.318-mhz crystal. if using an external reference, this pin must be left unconnected. ref_2x/fs2 48 i/o reference clock/frequency select 2: 3.3v 14.318-mhz clock output. this pin also serves as a power-on strap option to determine device operating frequency as described in the frequency selection table. multsel0 38 i current multiplier selection 0: 3.3v input to select the current multiplier for cpu clock outputs. the multsel0 is as follows: multsel0 0 = ioh is 4 iref 1 = ioh is 6 iref cpu0:2, cpu0:2# 47, 44, 40, 46, 43,39 o cpu clock outputs: frequency is set by the fs0:4 inputs or through serial input interface. 3v66_1:3 20, 21, 22 o 66mhz clock outputs: 3.3v 66-mhz clock. 3v66_0/vch_clk/f s4 31 i/o 66mhz clock output/ frequency select 4: 3.3v 66-mhz or 48-mhz clock output. the selection is determined by the control byte register. this pin also serves as a power-on strap option to determine device operating frequency as described in the frequency selection table. pci_f0/fs0 5 i/o free-running pci output 0/frequency select 0: 3.3v free-running pci output. this pin also serves as a power-on strap option to determine device operating frequency as described in the frequency selection table. pci_f1/fs1 6 i/o free-running pci output 1/frequency select 1: 3.3v free-running pci output. this pin also serves as a power-on strap option to determine device operating frequency as described in the frequency selection table. pci0:6 9, 10, 11, 12, 15, 16, 17 o pci clock output 0 to 6: 3.3v pci clock outputs. 48mhz/fs3 35 i/o 48mhz output/frequency select 3: 3.3v fixed 48-mhz, non-spread spectrum output. this pin also serves as a power-on strap option to determine device operating frequency as described in the frequency selection table. 24_48mhz 34 i/o 24 or 48mhz output: 3.3v fixed 24-mhz or 48-mhz non-spread spectrum output. sclk 28 i smbus clock input: clock pin for serial interface. sdata 27 i/o smbus data input: data pin for serial interface. rst# 23 o (open- drain) system reset output: open-drain system reset output. iref 37 i current reference for cpu output: a precision resistor is attached to this pin, which is connected to the internal current reference. vtt_pwrgd/pd# 26 i powergood from voltage regulator module (vrm)/pd#: 3.3v lvttl input. vtt_pwrgd# is a level sensitive strobe used to determine when fs0:4 and multsel0 inputs are valid and ok to be sampled (active high). vdd_ref, vdd _pci, vdd_48mhz, vdd_3v66, vdd_cpu 1, 7, 13, 18, 30, 33, 41, 45 p 3.3v power connection: power supply for cpu outputs buffers, 3v66 output buffers, pci output buffers, reference output buffers and 48-mhz output buffers. connect to 3.3v. vdd_48mhz 33 p 3.3v power connection: 48mhz output buffers. connect to 3.3v. gnd_pci, gnd_48mhz, gnd_3v66, gnd_cpu, gnd_ref, 4, 8, 14, 19, 29, 32, 36, 42 g ground connection: connect all ground pins to the common system ground plane.
cy28344 rev 1.0, november 21, 2006 page 3 of 21 vdd_core 24 p 3.3v analog power connection: power supply for core logic, pll circuitry. connect to 3.3v. gnd_core 25 g analog ground connection: ground for core logic, pll circuitry. pin definitions (continued) pin name pin no. pin type pin description swing select functions (sw control) sw_multsel1 sw_multsel0 board target trace/term z reference r, iref = vdd/(3*rr) output current v oh @ z 0 0 50 ohm rr = 221 1%, iref = 5.00 ma i oh = 4*iref 1.0v @ 50 0 0 60 ohm rr = 221 1%, iref = 5.00 ma i oh = 4*iref 1.2v @ 60 0 1 50 ohm rr = 221 1%, iref = 5.00 ma i oh = 5*iref 1.25v @ 50 0 1 60 ohm rr = 221 1%, iref = 5.00 ma i oh = 5*iref 1.5v @ 60 1 0 50 ohm rr = 221 1%, iref = 5.00 ma i oh = 6*iref 1.5v @ 50 1 0 60 ohm rr = 221 1%, iref = 5.00 ma i oh = 6*iref 1.8v @ 60 1 1 50 ohm rr = 221 1%, iref = 5.00 ma i oh = 7*iref 1.75v @ 50 1 1 60 ohm rr = 221 1%, iref = 5.00 ma i oh = 7*iref 2.1v @ 60 0 0 50 ohm rr = 475 1%, iref = 2.32 ma i oh = 4*iref 0.47v @ 50 0 0 60 ohm rr = 475 1%, iref = 2.32 ma i oh = 4*iref 0.56v @ 60 0 1 50 ohm rr = 475 1%, iref = 2.32 ma i oh = 5*iref 0.58v @ 50 0 1 60 ohm rr = 475 1%, iref = 2.32 ma i oh = 5*iref 0.7v @ 60 1 0 50 ohm rr = 475 1%, iref = 2.32 ma i oh = 6*iref 0.7v @ 50 1 0 60 ohm rr = 475 1%, iref = 2.32 ma i oh = 6*iref 0.84v @ 60 1 1 50 ohm rr = 475 1%, iref = 2.32 ma i oh = 7*iref 0.81v @ 50 1 1 60 ohm rr = 475 1%, iref = 2.32 ma i oh = 7*iref 0.97v @ 60 swing select functions (hw control) multsel0 board target trace/term z reference r, iref = vdd/(3*rr) output current v oh @ z 0 50 ohm rr = 221 1%, iref = 5.00 ma i oh = 4*iref 1.0v @ 50 0 60 ohm rr = 221 1%, iref = 5.00 ma i oh = 4*iref 1.2v @ 60 1 50 ohm rr = 221 1%, iref = 5.00 ma i oh = 6*iref 1.5v @ 50 1 60 ohm rr = 221 1%, iref = 5.00 ma i oh = 6*iref 1.8v @ 60
cy28344 rev 1.0, november 21, 2006 page 4 of 21 serial data interface to enhance the flexibility and function of the clock synthesizer, a two signal serial interface is provided. through the serial data interface, various device functions such as individual clock output buffers, etc. can be individually enabled or disabled. the registers associated with the serial data interface initializes to it?s default setting upon power-up, and therefore use of this interface is optional. clock device register changes are normally made upon system initialization, if any are required. the interface can also be used during system operation for power management functions. data protocol the clock driver serial protocol accepts byte write, byte read, block write and block read operation from the controller. for block write/read operation, the bytes must be accessed in sequential order from lowest to highest byte (most significant bit first) with the ability to stop after any complete byte has been transferred. for byte write and byte read operations, the system controller can access individual indexed bytes. the offset of the indexed byte is encoded in the command code, as described in table 1 . the block write and block read protocol is outlined in table 2 while ta ble 3 outlines the corresponding byte write and byte read protocol. the slave receiver address is 11010010 (d2h). table 1. command code definition bit descriptions 7 0 = block read or block write operation 1 = byte read or byte write operation 6:0 byte offset for byte read or byte write operation. for block read or block write operations, these bits should be ?0000000? table 2. block read and block write protocol block write protocol block read protocol bit description bit description 1start 1start 2:8 slave address ? 7 bit 2:8 slave address ? 7 bit 9write 9write 10 acknowledge from slave 10 acknowledge from slave 11:18 command code ? 8 bit ?00000000? stands for block operation 11:18 command code ? 8 bit ?00000000? stands for block operation 19 acknowledge from slave 19 acknowledge from slave 20:27 byte count ? 8 bits 20 repeat start 28 acknowledge from slave 21:27 slave address ? 7 bits 29:36 data byte 0 ? 8 bits 28 read 37 acknowledge from slave 29 acknowledge from slave 38:45 data byte 1 ? 8 bits 30:37 byte count from slave ? 8 bits 46 acknowledge from slave 38 acknowledge ... data byte n/slave acknowledge... 39:46 data byte from slave ? 8 bits ... data byte n ? 8 bits 47 acknowledge ... acknowledge from slave 48:55 data byte from slave ? 8 bits ... stop 56 acknowledge ... data bytes from slave/acknowledge ... data byte n from slave ? 8 bits ... not acknowledge ... stop
cy28344 rev 1.0, november 21, 2006 page 5 of 21 data byte configuration map table 3. byte read and byte write protocol byte write protocol byte read protocol bit description bit description 1start 1start 2:8 slave address ? 7 bit 2:8 slave address ? 7 bit 9write 9write 10 acknowledge from slave 10 acknowledge from slave 11:18 command code ? 8 bit ?1xxxxxxx? stands for byte operation bit[6:0] of the command code represents the offset of the byte to be accessed 11:18 command code ? 8 bit ?1xxxxxxx? stands for byte operation bit[6:0] of the command code represents the offset of the byte to be accessed 19 acknowledge from slave 19 acknowledge from slave 20:27 data byte ? 8 bits 20 repeat start 28 acknowledge from slave 21:27 slave address ? 7 bits 29 stop 28 read 29 acknowledge from slave 30:37 data byte from slave ? 8 bits 38 not acknowledge 39 stop data byte 0 bit pin# name description power on default bit 7 -- sel3 sw frequency selection bits. see table 4 .0 bit 6 -- sel2 0 bit 5 -- sel1 0 bit 4 -- sel0 0 bit 3 -- fs_override 0 = select operating frequency by fs[4:0] input pins 1 = select operating frequency by sel[4:0] settings 0 bit 2 -- sel4 sw frequency selection bits. see table 4 .0 bit 1 -- spread spectrum enable 0 = off; 1 = enabled 0 bit 0 -- reserved reserved 0 data byte 1 bit pin# name description power on default bit 7 40, 39 cpu2, cpu2# (active/inactive) 1 bit 6 44, 43 cpu1, cpu1# (active/inactive) 1 bit 5 47, 46 cpu0, cpu0# (active/inactive) 1 bit 4 -- latched fs4 input latched fs[4:0] inputs. these bits are read-only. x bit 3 -- latched fs3 input x bit 2 -- latched fs2 input x bit 1 -- latched fs1 input x bit 0 -- latched fs0 input x
cy28344 rev 1.0, november 21, 2006 page 6 of 21 data byte 2 bit pin# name pin description power on default bit 7 -- reserved reserved 0 bit 6 17 pci6 (active/inactive) 1 bit 5 16 pci5 (active/inactive) 1 bit 4 15 pci4 (active/inactive) 1 bit 3 12 pci3 (active/inactive) 1 bit 2 11 pci2 (active/inactive) 1 bit 1 10 pci1 (active/inactive) 1 bit 0 9 pci0 (active/inactive) 1 data byte 3 bit pin# name pin description power on default bit 7 34 24_48mhz (active/inactive) 1 bit 6 35 48mhz (active/inactive) 1 bit 5 -- reserved reserved 0 bit 4 -- reserved reserved 0 bit 3 31 3v66_0/vch_clk 0 = 66 mhz; 1 = 48 mhz 0 bit 2 31 3v66_0/vch_clk (active/inactive) 1 bit 1 6 pci_f1 (active/inactive) 1 bit 0 5 pci_f0 (active/inactive) 1 data byte 4 bit pin# name pin description power on default bit 7 -- multsel_override this bit control the selection of iref multiple. 0 = hw control; iref multiplier is determined by multsel[0:1] input pins 1 = sw control; iref multiplier is determined by byte[4], bit[5:6]. 0 bit 6 -- sw_multsel1 iref multiplier 00 = ioh is 4 iref 01 = ioh is 5 iref 10 = ioh is 6 iref 11 = ioh is 7 iref 0 bit 5 -- sw_multsel0 0 bit 4 48 ref_2x (active/inactive) drive 1 bit 3 -- ref_drv 0 = normal, 1 = high 0 bit 2 22 3v66_3 (active/inactive) 1 bit 1 21 3v66_2 (active/inactive) 1 bit 0 20 3v66_1 (active/inactive) 1
cy28344 rev 1.0, november 21, 2006 page 7 of 21 data byte 5 bit pin# name pin description power on default bit 7 -- spread option 1 ?00? = 0.25% ?01? = ? 0.5% ?10? = 0.5% ?11? = 0.38% 0 bit 6 -- spread option 0 0 bit 5 -- reserved reserved 0 bit 4 -- reserved reserved 0 bit 3 -- reserved reserved 0 bit 2 -- reserved reserved 0 bit 1 -- reserved reserved 0 bit 0 34 24_ 48mhz 0 = 24 mhz 1 = 48 mhz 1 data byte 6 bit pin# name pin description power on default bit 7 revision_id3 revision id bit[3] 0 bit 6 revision_id2 revision id bit[2] 0 bit 5 revision_id1 revision id bit[1] 0 bit 4 revision_id0 revision id bit[0] 0 bit 3 vendor_id3 bit[3] of cypress vendor id. this bit is read-only. 1 bit 2 vendor_id2 bit[2] of cypress vendor id. this bit is read-only. 0 bit 1 vendor _id1 bit[1] of cypress vendor id. this bit is read-only. 0 bit 0 vendor _id0 bit[0] of cypress vendor id. this bit is read-only. 0 data byte 7 bit pin# name pin description power on default bit 7 -- reserved reserved 0 bit 6 -- reserved reserved 0 bit 5 -- reserved reserved 0 bit 4 -- reserved reserved 0 bit 3 -- reserved reserved 0 bit 2 -- reserved reserved 0 bit 1 -- reserved reserved 0 bit 0 -- reserved reserved 0 data byte 8 bit pin# name pin description power on default bit 7 -- reserved reserved 0 bit 6 -- reserved reserved 0
cy28344 rev 1.0, november 21, 2006 page 8 of 21 bit 5 -- wd_timer4 these bits store the time-out value of the watchdog timer. the scale of the timer is determine by the pre-scaler. the timer can support values from 150 ms ? 4.8 sec when the pre-scaler is set to 150 ms. if the pre-scaler is set to 2.5 sec, it can support a value from 2.5 ? 80 seconds. when the watchdog timer reaches ?0?, it will set the wd_to_status bit and generate reset if rst_en_wd is enabled. 1 bit 4 -- wd_timer3 1 bit 3 -- wd_timer2 1 bit 2 -- wd_timer1 1 bit 1 -- wd_timer0 1 bit 0 -- wd_pre_scaler 0 = 150 ms 1 = 2.5 sec 0 data byte 8 (continued) bit pin# name pin description power on default data byte 9 bit pin# name pin description power on default bit 7 -- 48mhz_drv 48mhz and 24_48mhz clock output drive strength 0 = normal 1 = high drive 0 bit 6 -- pci_drv pci clock output drive strength 0 = normal 1 = high drive 0 bit 5 -- 3v66_drv 3v66 clock output drive strength 0 = normal 1 = high drive 0 bit 4 -- rst_en_wd this bit will enable the generation of a reset pulse when a watchdog timer time-out occurs. 0 = disabled 1 = enabled 0 bit 3 -- rst_en_fc this bit will enable the generation of a reset pulse after a frequency change occurs. 0 = disabled 1 = enabled 0 bit 2 -- wd_to_status watchdog timer time-out status bit 0 = no time-out occurs (read); ignore (write) 1 = time-out occurred (read); clear wd_to_status (write) 0 bit 1 -- wd_en 0 = stop and re-load watchdog timer 1 = enable watchdog timer. it will start counting down after a frequency change occurs. note : cy28344 will generate system reset, reload a recovery frequency, and lock itself into a recovery frequency mode after a watchdog timer time-out occurs. under recovery frequency mode, cy28344 will not respond to any attempt to change output frequency via the smbus control bytes. system software can unlock cy28344 from its recovery frequency mode by clearing the wd_en bit. 0 bit 0 -- reserved reserved 0
cy28344 rev 1.0, november 21, 2006 page 9 of 21 data byte 10 bit pin# name pin description power on default bit 7 -- cpu_skew2 cpu skew control 000 = normal 001 = ?150 ps 010 = ?300 ps 011 = ?450 ps 100 = +150 ps 101 = +300 ps 110 = +450 ps 111 = +600 ps 0 bit 6 -- cpu_skew1 0 bit 5 -- cpu_skew0 0 bit 4 -- reserved reserved 0 bit 3 -- pci_skew1 pci skew control 00 = normal 01 = ?500 ps 10 = reserved 11 = +500 ps 0 bit 2 -- pci_skew0 0 bit 1 -- 3v66_skew1 3v66 skew control 00 = normal 01 = ?150 ps 10 = +150 ps 11 = +300 ps 0 bit 0 -- 3v66_skew0 0 data byte 11 bit pin# name pin description power on default bit 7 -- rocv_freq_n7 if rocv_freq_sel is set, the values programmed in rocv_freq_n[7:0] and rocv_freq_m[6:0] will be used to determine the recovery cpu output frequency when a watchdog timer time-out occurs. the setting of fs_override bit determines the frequency ratio for cpu and other output clocks. when fs_override bit is cleared, the same frequency ratio stated in the latched fs[4:0] register will be used. when it is set, the frequency ratio stated in the sel[4:0] register will be used. 0 bit 6 -- rocv_freq_n6 0 bit 5 -- rocv_freq_n5 0 bit 4 -- rocv_freq_n4 0 bit 3 -- rocv_freq_n3 0 bit 2 -- rocv_freq_n2 0 bit 1 -- rocv_freq_n1 0 bit 0 -- rocv_freq_n0 0 data byte 12 bit pin# name pin description power on default bit 7 -- rocv_freq_sel rocv_freq_sel determines the source of the recover frequency when a watchdog timer time-out occurs. the clock generator will automatically switch to the recovery cpu frequency based on the selection on rocv_freq_sel. 0 = from latched fs[4:0] 1 = from the settings of rocv_freq_n[7:0] and rocv_freq_m[6:0] 0
cy28344 rev 1.0, november 21, 2006 page 10 of 21 bit 6 -- rocv_freq_m6 if rocv_freq_sel is set, the values programmed in rocv_freq_n[7:0] and rocv_freq_m[6:0] will be used to determine the recovery cpu output frequency.when a watchdog timer time-out occurs. the setting of fs_override bit determine the frequency ratio for cpu and other output clocks. when fs_override bit is cleared, the same frequency ratio stated in the latched fs[4:0] register will be used. when it is set, the frequency ratio stated in the sel[4:0] register will be used. 0 bit 5 -- rocv_freq_m5 0 bit 4 -- rocv_freq_m4 0 bit 3 -- rocv_freq_m3 0 bit 2 -- rocv_freq_m2 0 bit 1 -- rocv_freq_m1 0 bit 0 -- rocv_freq_m0 0 data byte 12 (continued) bit pin# name pin description power on default data byte 13 bit pin# name pin description power on default bit 7 -- cpu_fsel_n7 if prog_freq_en is set, the values programmed in cpu_fsel_n[7:0] and cpu_fsel_m[6:0] will be used to determine the cpu output frequency. the new frequency will start to load whenever cpu_fselm[6:0] is updated. the setting of fs_override bit determines the frequency ratio for cpu and other output clocks. when it is cleared, the same frequency ratio stated in the latched fs[4:0] register will be used. when it is set, the frequency ratio stated in the sel[4:0] register will be used. 0 bit 6 -- cpu_fsel_n6 0 bit 5 -- cpu_fsel_n5 0 bit 4 -- cpu_fsel_n4 0 bit 3 -- cpu_fsel_n3 0 bit 2 -- cpu_fsel_n2 0 bit 1 -- cpu_fsel_n1 0 bit 0 -- cpu_fsel_n0 0 data byte 14 bit pin# name pin description power on default bit 7 -- pro_freq_en programmable output frequencies enabled 0 = disabled 1 = enabled 0 bit 6 -- cpu_fsel_m6 if prog_freq_en is set, the values programmed in cpu_fsel_n[7:0] and cpu_fsel_m[6:0] will be used to determine the cpu output frequency. the new frequency will start to load whenever cpu_fselm[6:0] is updated. the setting of fs_override bit determines the frequency ratio for cpu and other output clocks. when it is cleared, the same frequency ratio stated in the latched fs[4:0] register will be used. when it is set, the frequency ratio stated in the sel[4:0] register will be used. 0 bit 5 -- cpu_fsel_m5 0 bit 4 -- cpu_fsel_m4 0 bit 3 -- cpu_fsel_m3 0 bit 2 -- cpu_fsel_m2 0 bit 1 -- cpu_fsel_m1 0 bit 0 -- cpu_fsel_m0 0 data byte 15 bit pin# name pin description power on default bit 7 -- reserved reserved 0 bit 6 -- reserved reserved 0 bit 5 -- reserved reserved 0 bit 4 -- reserved reserved 0 bit 3 -- reserved reserved 0 bit 2 -- reserved reserved 0 bit 1 -- vendor test mode reserved. write with ?1? 1 bit 0 -- vendor test mode reserved. write with ?1? 1
cy28344 rev 1.0, november 21, 2006 page 11 of 21 data byte 16 bit pin# name pin description power on default bit 7 -- reserved reserved 0 bit 6 -- reserved reserved 0 bit 5 -- reserved reserved 0 bit 4 -- reserved reserved 0 bit 3 -- reserved reserved 0 bit 2 -- reserved reserved 0 bit 1 -- reserved reserved 0 bit 0 -- reserved reserved 0 data byte 17 bit pin# name pin description power on default bit 7 -- reserved reserved 0 bit 6 -- reserved reserved 0 bit 5 -- reserved reserved 0 bit 4 -- reserved reserved 0 bit 3 -- reserved reserved 0 bit 2 -- reserved reserved 0 bit 1 -- reserved reserved 0 bit 0 -- reserved reserved 0
cy28344 rev 1.0, november 21, 2006 page 12 of 21 table 4. frequency selection table input conditions output frequency pll gear constants (g) fs4 fs3 fs2 fs1 fs0 cpu 3v66 pci sel4 bit[2] sel3 bit[7] sel2 bit[6] sel1 bit[5] sel0 bit[4] 0 0 0 0 0 100.90 67.27 33.63 48.00741 0 0 0 0 1 100.00 66.67 33.33 48.00741 0 0 0 1 0 103.00 68.67 34.33 48.00741 0 0 0 1 1 105.00 70.00 35.00 48.00741 0 0 1 0 0 107.00 71.33 35.67 48.00741 0 0 1 0 1 109.00 72.67 36.33 48.00741 0 0 1 1 0 111.00 74.00 37.00 48.00741 0 0 1 1 1 114.00 76.00 38.00 48.00741 0 1 0 0 0 117.00 78.00 39.00 48.00741 0 1 0 0 1 120.00 80.00 40.00 48.00741 0 1 0 1 0 127.00 84.67 42.33 48.00741 0 1 0 1 1 130.00 86.67 43.33 48.00741 0 1 1 0 0 133.33 88.89 44.44 48.00741 0 1 1 0 1 170.00 56.67 28.33 48.00741 0 1 1 1 0 180.00 60.00 30.00 48.00741 0 1 1 1 1 190.00 63.33 31.67 48.00741 1 0 0 0 0 133.90 66.95 33.48 48.00741 1 0 0 0 1 133.33 66.67 33.33 48.00741 1 0 0 1 0 120.00 60.00 30.00 48.00741 1 0 0 1 1 125.00 62.50 31.25 48.00741 1 0 1 0 0 134.90 67.45 33.73 48.00741 1 0 1 0 1 137.00 68.50 34.25 48.00741 1 0 1 1 0 139.00 69.50 34.75 48.00741 1 0 1 1 1 141.00 70.50 35.25 48.00741 1 1 0 0 0 143.00 71.50 35.75 48.00741 1 1 0 0 1 145.00 72.50 36.25 48.00741 1 1 0 1 0 150.00 75.00 37.50 48.00741 1 1 0 1 1 155.00 77.50 38.75 48.00741 1 1 1 0 0 160.00 80.00 40.00 48.00741 1 1 1 0 1 170.00 85.00 42.50 48.00741 1 1 1 1 0 66.67 66.67 33.34 48.00741 1 1 1 1 1 200.00 66.67 33.33 48.00741
cy28344 rev 1.0, november 21, 2006 page 13 of 21 programmable output frequency, watchdog timer and recovery output frequency functional description the programmable output frequency feature allows users to generate any cpu output frequency from the range of 50 ? 248 mhz. cypress offers the most dynamic and the simplest programming interface for system developers to utilize this feature in their platforms. the watchdog timer and recovery output frequency features allow users to implement a recovery mechanism when the system hangs or getting unstable. system bios or other control software can enable the watchdog timer before they attempt to make a frequency change. if the system hangs and a watchdog timer time-out occurs, a system reset will be generated and a recovery frequency will be activated. all the related registers are summarized in the following table. table 5. register summary name description pro_freq_en programmable output frequencies enabled 0 = disabled (default) 1 = enabled when it is disabled, the operating output frequency will be determined by either the latched value of fs[4:0] inputs or the programmed value of sel[4:0]. if fs_override bit is clear, latched fs[4:0] inputs will be used. if fs_override bit is set, programmed value of sel[4:0] will be used. when it is enabled, the cpu output frequency will be determined by the programmed value of cpufsel_n, cpufsel_m and the pll gear constant. the program value of fs_override, sel[4:0] or the latched value of fs[4:0] will determine the pll gear constant and the frequency ratio between cpu and other frequency outputs. fs_override when pro_freq_en is cleared or disabled, 0 = select operating frequency by fs input pins (default) 1 = select operating frequency by sel bits in smbus control bytes when pro_freq_en is set or enabled, 0 = frequency output ratio between cpu and other frequency groups and the pll gear constant are based on the latched value of fs input pins (default) 1 = frequency output ratio between cpu and other frequency groups and the pll gear constant are based on the programmed value of sel bits in smbus control bytes cpu_fsel_n, cpu_fsel_m when prog_freq_en is set or enabled, the values programmed in cpu_fsel_n[7:0] and cpu_fsel_m[6:0] determines the cpu output frequency. the new frequency will start to load whenever there is an update to either cpu_fsel_n[7:0] or cpu_fsel_m[6:0]. therefore, it is recom- mended to use word or block write to update both registers within the same smbus bus operation. the setting of fs_override bit determines the frequency ratio for cpu, agp and pic. when fs_override is cleared or disabled, the frequency ratio follows the latched value of the fs input pins. when fs_override is set or enabled, the frequency ratio follows the programmed value of sel bits in smbus control bytes. rocv_freq_sel rocv_freq_sel determines the source of the recover frequency when a watchdog timer time-out occurs. the clock generator will automatically switch to the recovery cpu frequency based on the selection on rocv_freq_sel. 0 = from latched fs[4:0] 1 = from the settings of rocv_freq_n[7:0] and rocv_freq_m[6:0] rocv_freq_n[7:0], rocv_freq_m[6:0] when rocv_freq_sel is set, the values programmed in rocv_freq_n[7:0] and rocv_freq_m[6:0] will be used to determine the recovery cpu output frequency when a watchdog timer time-out occurs. the setting of fs_override bit determines the frequency ratio for cpu, agp and pic. when it is cleared, the same frequency ratio stated in the latched fs[4:0] register will be used. when it is set, the frequency ratio stated in the sel[4:0] register will be used. the new frequency will start to load whenever there is an update to either rocv_freq_n[7:0] and rocv_freq_m[6:0]. therefore, it is recommended to use word or block write to update both registers within the same smbus bus operation. wd_en 0 = stop and re-load watchdog timer 1 = enable watchdog timer. it will start counting down after a frequency change occurs. wd_to_status watchdog timer time-out status bit 0 = no time-out occurs (read); ignore (write) 1 = time-out occurred (read); clear wd_to_status (write)
cy28344 rev 1.0, november 21, 2006 page 14 of 21 program the cpu output frequency when the programmable output frequency feature is enabled (pro_freq_en bit is set), the cpu output frequency is deter- mined by the following equation: fcpu = g * (n+3)/(m+3). ?n? and ?m? are the values programmed in programmable frequency select n-value register and m-value register, respectively. ?g? stands for the pll gear constant, which is determined by the programmed value of fs[4:0] or sel[4:0]. the value is listed in table 4 . the ratio of (n+3) and (m+3) needs to be greater than ?1? [(n+3)/(m+3) > 1]. the following table lists set of n and m values for different frequency output ranges.this example uses a fixed value for the m-value register and select the cpu output frequency by changing the value of the n-value register. wd_timer[4:0] these bits store the time-out value of the watchdog timer. the scale of the timer is determined by the prescaler. the timer can support a value of 150 ms ? 4.8 sec when the prescaler is set to 150 ms. if the prescaler is set to 2.5 sec, it can support a value from 2.5 sec ? 80 sec. when the watchdog timer reaches ?0,? it will set the wd_to_status bit. wd_pre_scaler 0 = 150 ms 1 = 2.5 sec rst_en_wd this bit will enable the generation of a reset pulse when a watchdog timer time-out occurs. 0 = disabled 1 = enabled rst_en_fc this bit will enable the generation of a reset pulse after a frequency change occurs. 0 = disabled 1 = enabled table 5. register summary (continued) name description table 6. examples of n and m value for different cpu frequency range frequency ranges gear constants f ixed value for m-value register range of n-value register for different cpu frequency 50 mhz ? 129 mhz 48.00741 93 97 ? 255 130 mhz ? 248 mhz 48.00741 45 127 ? 245
cy28344 rev 1.0, november 21, 2006 page 15 of 21 maximum ratings [2] (above which the useful life may be impaired. for user guide- lines, not tested.) supply voltage..................................................?0.5 to +7.0v input voltage.............................................. ?0.5v to v dd +0.5 storage temperature (non-condensing) ....?65 q c to +150 q c max. soldering temperature (10 sec) ..... .............. .... +260 q c junction temperature................................................ +150 q c package power dissipation.......... .............. .............. ......... 1 : static discharge voltage (per mil-std-883, method 3015) ............................ > 2000v operating conditions over which electrical parameters are guaranteed parameter description min. max. unit v dd_ref , v dd_pci ,vdd_core, v dd_3v66 ,v dd_48 mhz, v dd_cpu, 3.3v supply voltages 3.135 3.465 v v dd_48 mhz 48 mhz supply voltage 2.85 3.465 v t a operating temperature, ambient 0 70 q c c in input pin capacitance 5 pf c xtal xtal pin capacitance 22.5 pf c l max. capacitive load on 48 mhz, ref pciclk, 3v66 20 30 pf f (ref) reference frequency, oscillator nominal value 14.318 14.318 mhz electrical characteristics over the operating range parameter description test conditions min. max. unit v ih high-level input voltage except crystal pads. threshold voltage for crystal pads = v dd /2 2.0 v v il low-level input voltage except crystal pads 0.8 v v oh high-level output voltage 48 mhz, ref, 3v66 i oh = ?1 ma 2.4 v pci i oh = ?1 ma 2.4 v v ol low-level output voltage 48 mhz, ref, 3v66 i ol = 1 ma 0.4 v pci i ol = 1 ma 0.55 v i ih input high current 0 < v in < v dd ?5 5 ma i il input low current 0 < v in < v dd ?5 5 ma i oh high-level output current cpu for i oh = 6*iref configuration type x1, v oh = 0.65v 12.9 ma type x1, v oh = 0.74v 14.9 ref, 48 mhz type 3, v oh = 1.00v ?29 type 3, v oh = 3.135v ?23 3v66, pci type 5, v oh = 1.00v ?33 type 5, v oh = 3.135v ?33 i ol low-level output current ref, 48 mhz type 3, v ol = 1.95v 29 ma type 3, v ol = 0.4v 27 3v66, pci, type 5, v ol =1.95 v 30 type 5, v ol = 0.4v 38 i oz output leakage current three-state 10 ma i dd3 3.3v power supply current vdd_core/vdd3.3 = 3.465v, f cpu = 133 mhz 250 ma i ddpd3 3.3v shutdown current vdd_core/vdd3.3 = 3.465v 20 ma note: 2. the voltage on any input or any i/o pin cannot exceed the power pin during power-up. power supply sequencing is not required.
cy28344 rev 1.0, november 21, 2006 page 16 of 21 - switching characteristics [3] over the operating range, pci,3v66 clock outputs.(lump capacitancetest load = 20 pf) parameter output description test conditions min. max. unit t 1 all output duty cycle [4] measured at 1.5v 45 55 % t 3 usb, ref, dot falling edge rate between 2.4v and 0.4v 0.5 2.0 ps t 3 pci,3v66 falling edge rate between 2.4v and 0.4v 1.0 4.0 v/ns t 5 3v66[0:1] 3v66-3v66 skew measured at 1.5v 500 ps t 5 66buff[0:2] 66buff-66buff skew measured at 1.5v 175 ps t 6 pci pci-pci skew measured at 1.5v 500 ps t 7 3v66,pci 3v66-pci clock jitter 3v66 leads. measured at 1.5v 1.5 3.5 ns t 9 3v66 cycle-cycle clock jitter measured at 1.5v t 9 = t 9a ? t 9b 250 ps t 9 usb, dot cycle-cycle clock jitter measured at 1.5v t 9 = t 9a ? t 9b 350 ps t 9 pci cycle-cycle clock jitter measured at 1.5v t 9 = t 9a ? t 9b 500 ps t 9 ref cycle-cycle clock jitter measured at 1.5v t 9 = t 9a ? t 9b 1000 ps cpu 1.0v switching characteristics t 2 cpu risetime measured differential waveform from ?0.35v to +0.35v 175 467 ps t 3 cpu fall time measured differential waveform from ?0.35v to +0.35v 175 467 ps t 4 cpu cpu-cpu skew measured at crossover 150 ps t 8 cpu cycle-cycle clock jitter measured at crossover t 8 = t 8a ? t 8b 150 ps cpu rise/fall matching measured with test loads [5] 325 mv v oh cpu high-level output voltage including overshoot measured with test loads [5] 0.92 1.45 v v ol cpu low-level output voltage including undershoot measured with test loads [5] -0.2 0.35 v v crossover cpu crossover voltage measured with test loads [5] 0.51 0.76 v cpu 0.7v switching characteristics t 2 cpu risetime measured single ended waveform from 0.175v to 0.525v 175 700 ps t 3 cpu fall time measured single ended waveform from 0.175v to 0.525v 175 700 ps t 4 cpu cpu-cpu skew measured at crossover 150 ps t 8 cpu cycle-cycle clock jitter measured at crossover t 8 = t 8a ? t 8b with all outputs running 150 ps cpu rise/fall matching measured with test loads [3,4] 20 % v oh cpu high-level output voltage including overshoot measured with test loads [4] 0.85 v v ol cpu low-level output voltage including undershoot measured with test loads [4] -0.15 v v crossover cpu crossover voltage measured with test loads [4] 0.28 0.43 v notes: 3. all parameters specified with loaded outputs. 4. duty cycle is measured at 1.5v when v dd = 3.3v. when v dd = 2.5v, duty cycle is measured at 1.25v. 5. determined as a fraction of 2*(trp ? trn)/(trp +trn) where trp is a rising edge and trp is an intersecting falling edge. 6. the 0.7v test load is r s = 33.2 ohm, r p = 49.9 ohm in test circuit. 7. the 1.0v test load is shown on test circuit page.
cy28344 rev 1.0, november 21, 2006 page 17 of 21 switching waveforms duty cycle timing t 1b (single-ended output) t 1a duty cycle timing (cpu differential output) t 1b t 1a all outputs rise/fall time output t 2 v dd 0v t 3 cpu-cpu clock skew host_b host t 4 host_b host 3v66-3v66 clock skew 3v66 3v66 t 5
cy28344 rev 1.0, november 21, 2006 page 18 of 21 switching waveforms (continued) pci-pci clock skew pci pci t 6 3v66 pci t 7 3v66-pci clock skew t 8a t 8b cpu clock cycle-cycle jitter host_b host t 9a t 9b cycle-cycle clock jitter clk
cy28344 rev 1.0, november 21, 2006 page 19 of 21 layout example 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 6 7 13 19 20 24 1 2 3 4 5 8 9 11 12 14 15 16 17 22 23 21 32 31 18 33 10 28 27 26 25 29 30 fb +3.3v supply c2 10 p f fb = dale ilb1206 ? 300 or 2tdkacb2012l ? 120 or 2 murata blm21b601s 0.005 p f g g vddq3 c1 g v g v g v g v g v g g vddq3 c5 c6 : g v g g g g g v *option b cy28344 g g g g g g g g g g g core g v g *option a g ceramic caps c1 = 10 ? 22 p f c2 = 0.005 p f c5 = 0.1 p f c6 = 10 p f g = via to gnd plane layer v = via to respective supply plane layer note. each supply plane or strip should have a ferrite bead and capacitors. * if on-board video uses 48 mhz or dot clock uses option b all bypass caps on v dd pin = 0.1 uf low esr
cy28344 rev 1.0, november 21, 2006 page 20 of 21 test circuit note: all capacitors must be placed as close to the pins as is physically possible. 4, 8, 14, 19, 25, 29, 32, 36, 42 vdd_ref, vdd_pci, outputs note: each supply pin must have an individual decoupling capacitor. vdd_3v66, vdd_core vdd_48 mhz, vdd_cpu te s t nodes r s r s r p r p cpu ref,usb outputs pci,3v66 outputs 30 pf 20 pf test node test node 7, 13, 18, 24, 30, 33, 41, 45 0.7v amplitude: r s = 33 ohm, r p = 50 ohm 0.7v test load 2pf 2pf 4, 8, 14, 19, 25, 29, 32, 36, 42 vdd_ref, vdd_pci, outputs vdd_3v66, vdd_core vdd_48 mhz, vdd_cpu te s t nodes cpu ref,usb outputs pci,3v66 outputs 30 pf 20 pf test node test node 7, 13, 18, 24, 30, 33, 41, 45 1.0v test load 2pf 2pf 33 33 63.4 63.4 475 1.0v amplitude
rev 1.0, november 21, 2006 page 21 of 21 cy28344 while sli has reviewed all information herein for accuracy and reliability, spectra linear inc. assumes no responsibility for t he use of any cir- cuitry or for the infringement of any patents or other rights of third parties which would result from each use. this product i s intended for use in normal commercial applications and is not warranted nor is it intended for use in life support, critical medical instruments, o r any other applica- tion requiring extended temperature range, high reliability, or any other extraordinary environmental requirements unless pursu ant to additional processing by spectra linear inc., and expressed written agreement by spectra linear inc. spectra linear inc. reserves the righ t to change any circuitry or specification without notice. package drawing and dimensions ordering information ordering code package type operating range CY28344PVC 48-pin small shrunk outline package (ssop) commercial 48-lead shrunk small outline package o48 51-85061-b

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